The present invention relates to a demodulator for a four-phase modulated wave and, more particularly, to a Costas loop carrier wave reproducing circuit.
In general, a digital phase modulation scheme for carrier waves, called "PSK", is superior in its frequency band characteristics and code error rate characteristics to other modulation schemes such as amplitude modulation, frequency modulation, and pulse modulation, and hence is widely used in, e.g., PCM microwave communications, satellite communications, and data transmission modems.
This phase modulation scheme includes two-, four-, and eight-phase PSK schemes which can transmit 1-, 2-, and 3-bit data per one sampling period, respectively. The four-phase PSK scheme is most widely used in practice because a PSK scheme for more than four phases demands strict identification characteristics and the arrangement of the modulator becomes complicated.
In this four-phase PSK scheme, the digital code of a signal to be transmitted is divided for every two bits, and a carrier wave is modulated by a phase shift amount corresponding to one of the four combinations of 2-bit data. In many four-phase schemes currently used in practice, phase shift amounts of 0, .pi./2, .pi., and 2/3.pi. respectively correspond to the four combinations (0, 0), (0, 1), (1, 0), and (1, 1). According to this scheme, a 2-bit signal component is contained in an inphase component and an orthogonal component of a carrier wave. For this reason, in demodulation, the inphase and orthogonal components of the carrier wave are respectively detected to identify their polarities.
In this case, a synchronous detection scheme is often used as a detection scheme because it has good code error rate characteristics. Unlike other delay detection schemes, however, in the synchronous detection scheme, a carrier wave reproducing circuit must be prepared on the reception side to generate a carrier wave having a correct phase.
This carrier wave reproducing circuit is designed to control a phase-locked loop circuit (PLL) by using a signal obtained by removing a code component from an input carrier wave.
FIG. 3 is a block diagram showing the principle of a four-phase demodulating circuit. Referring to FIG. 3, reference numerals 1, 2, and 7 denote multipliers; 3, 4, and 8, LPFs (low-pass filters); 5, an adder; 6, a subtracter; 9, a VCXO; 10, a phase shifter; and 20, Costas loop carrier wave reproducing circuit.
A signal S as a four-phase modulated wave is represented by the following equation, provided that E is a magnitude, wt is the frequency of a carrier wave, and .theta. is a phase shift of 0, 90.degree., 180.degree., or 270.degree.: EQU S=Ecos(wt+.theta.) (1)
If two outputs (one of them is delayed by 2/.pi.) from the VCXO (voltage-controlled crystal oscillator) 9 are respectively represented by A and B, the following equations can be established: EQU A=E.sub.1 sin(wt+.theta..sub.1) (2) EQU B=E.sub.1 cos(wt+.theta..sub.1) (3)
When the four-phase modulated wave S and the oscillator outputs A and B are demodulated by the multipliers 1 and 2 and are filtered by the LPFs (low-pass filters) 3 and 4, the multiplication of equations (1) and (2) is rewritten as follows: ##EQU1##
If this equation is filtered by an LPF, the following expression is obtained: ##EQU2##
Similarly, the multiplication of equations (1) and (3) is represented by ##EQU3##
The outputs from the LPFs are then processed by the Costas loop carrier wave reproducing circuit 20. The circuit 20 serves to keep the phase of an output from the VCXO constant regardless of the phase state (0. 90.degree., 180.degree., 270.degree.) of an input four-phase modulated wave.
If the demodulated signals of equations (4) and (5) are respectively represented by P and Q, P+Q is output from an output E point of the adder 5; P-Q, from an output F point of the subtracter 6; and P.times.Q.times.(P+Q).times.(P-Q), from an output G point of the multiplier 7. At the output E, the following equations are established: ##EQU4##
At the output G point, the following equation can be obtained by the multiplication of equations (6) and (7: ##EQU5##
In this case, a phase difference (.theta.-.theta..sub.1) between the four-phase modulated wave, the output signal from the VCXO is n.pi./4, and the output voltage relatively becomes 0 (n=integer), and the PLL is locked in this
If, therefore, this output is fed back to the VCXO 9 through the LPF 8, the data of the signals P and Q are demodulated.
FIG. 2 is a circuit diagram showing the detailed arrangement of the conventional Costas loop carrier wave reproducing circuit 20 shown in FIG. 3. This conventional technique is disclosed in U.S.P. No. 4,694,204, Sep. 15, 1987, assigned to NEC Corporation. This circuit comprises a first multiplying circuit constituted by a double differential amplifier circuit consisting of transistors Q.sub.23 to Q.sub.28 and a constant current source I.sub.8, a second multiplying circuit constituted by a double differential amplifier circuit consisting of transistors Q.sub.33 to Q.sub.36 for receiving collector currents from the first multiplying circuit as common emitter currents, a fourth multiplying circuit constituted by a double differential amplifier circuit consisting of transistors Q.sub.33 to Q.sub.36 for receiving collector currents from the second multiplying circuit as common emitter currents, load resistors R.sub.11 and R.sub.12 for applying a collector current, as an output voltage, from the fourth multiplying circuit to output terminals a and b, three differential amplifiers, constituted by transistors Q.sub.1, Q.sub.2, Q.sub.21, Q.sub.37, and Q.sub.38, constant current sources I.sub.1, I.sub.7, and I.sub.9, and load resistors R.sub.13 and R.sub.16, for generating input voltages of the demodulated signals P and Q and their sum and difference signals, a bias circuit, constituted by DC power sources V.sub.1 and V.sub.2 and resistors R.sub.9 and R.sub.10, for biasing the three differential amplifiers, and a peripheral circuit constituted by DC power sources V.sub.3, V.sub.4, and V.sub.5.
Assume that the inphase demodulated signal P is input through a coupling capacitor C.sub.1. In this case, since the bases of the transistors Q.sub.1 and Q.sub.37 are biased by the bias power source V through, the bias resistor R.sub.9, and the bases of the transistors Q.sub.2 and Q.sub.38 are directly biased by the bias power source V.sub.1, a signal in phase with the inphase demodulated signal P appears at each of the load resistors R.sub.13 and R.sub.14. Similarly, if the orthogonal demodulated signal Q is input through a coupling capacitor C.sub.2, signals in phase with and in opposite phase to the demodulated signal Q appear at the load resistors R.sub.15 and R.sub.16 of the differential amplifier constituted by the transistors Q.sub.21 and Q.sub.22.
In the first multiplying circuit, the inphase demodulated signal P is input to the base of the transistor Q.sub.23, and the base of the transistor Q.sub.24 is biased by the DC power source V.sub.1, while a constant current I.sub.0 from the constant current source I.sub.8 flows in the commonly connected emitter. In this state, a current I.sub.CO and a current I.sub.CO which are in phase with and in opposite phase to the demodulated signal P respectively flow in the collectors of the transistors Q.sub.23 and Q.sub.24. In addition, the bases of the transistors Q.sub.25 and Q.sub.28 of the double amplifier circuit are biased by the DC power source V.sub.2, and the orthogonal demoudlated signal Q is input to the bases of the transistors Q.sub.26 and Q.sub.27, while the commonly connected emitted is controlled by the currents I.sub.CO and I.sub.CO which are in phase with and in opposite phase to the demoudlated singla P. Therefore, the sum of the collector currents of the transistors Q.sub.26 and Q.sub.28 become currents I.sub.D1 and I.sub.C2 corresponding to the product output (P.times.Q) of the two demodulated signals and an output in opposite phase thereto.
Subsequently, the product output currents I.sub.C1 and I.sub.C2 of the demoudlated signals P and Q respectively become common emitter curents flowing in the double amplifier circiut constituting the second multiplying circuit. In the double differential amplifier circiut of the second multiplying circiut, signals in phase with the demoulated signals P and Q are respectively supplied to the bases of the transistor sQ.sub.30 and Q.sub.31 in a differential manner through the load resistors R.sub.13 and R.sub.15. In this state, collector output currents I.sub.C3 and I.sub.C4 from the second multipolying circiut are proportional to values obtained by multipoying the product output (.times.Q) of the two demodulated signals P and Q by the signal (P-Q).
In the same manner as described above, these two collector output currents I.sub.C3 and I.sub.C4 become common emitter currents flowing in the double differential amplifier circiut constituting the third multiplying circiut. Since a signal in phase with the demoudlated signal P and a signal in opposite phase to the demodulated signal Q are differentially supplied to the bases of the transistors Q.sub.33 and Q.sub.36 of the double differential amplifier circiut of the third multiplying circiut through the load resistors R.sub.14 and R.sub.16, collector output currents I.sub.C5 and I.sub.C6 from the third multiplying circiut correspond to values obtained by multipoying the outputs from the second multiplying circiut by the signal {P-(-Q)}, i.e., the sum signal (P+Q).
WEith this operation, a voltage proportional to a voltage obtained by multplying all the four signals, i.e., the demudulated signals P and Q, the sum signal (P +Q), and the difference signal (P-Q), as the multiplication result obtained by the first to third multipolying circiuts, is output across output terminals a and b.
In this conventional Costas loop carrier wave reproducing circiut, the three double diferential mplifier circiuts are vertically stacked on each other to calculate P.times.Q.times. (P+Q).times.(P-Q). With this arrangement, in order to linearly operate the circiut, 4 .times.(VEB+amplitude)+a voltage drop due to the load resistors+a voltage required to normally operate the constant current sources is required as a power source voltage. In practice, however, if VBE=0.75 V, an amplitude=0.5 V.sub.pp, a voltage drop due to the load resistors=1 V, and a voltage applied to the constant current sources=1 V, V.sub.CC &gt;(0.75+0.5).times.4+1+1=7 V is required. Therefore, the circuit cannot be operated by a power source voltage of 5 V.